For high density recording or the like in the storage field of semiconductor memories and the like, development related to digital data error correcting codes is underway. The error correcting codes can be roughly divided into an error correcting scheme based on an algebraic system and an error correcting scheme using iterative calculation based on probability. Low density parity check codes (hereinafter referred to as “LDPC codes”) that belong to the latter are reported to have excellent performance nearing a Shannon limit.
LDPC-coded data can be subjected to parallel processing with a relatively small circuit scale by using a sum-product algorithm, a minisum algorithm or the like. However, applying complete parallel processing that performs all processing in parallel to LDPC-coded data of a large code length requires all of many operation circuits to be mounted, and is therefore not realistic.
For this reason, for example, Japanese Patent Application Laid-Open Publication No. 2006-279396 discloses a decoding apparatus that performs partial parallel processing using a check matrix having a configuration in which square matrixes are arranged.